This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-259232, filed on Aug. 29, 2000; the entire contents of which are incorporated herein by reference.
This invention relates to a DA converter, and more particularly, to a circuit for dividing a voltage depending on resistance components of a device and converting an input digital data to an analog value.
Various types of DA converter for converting digital data to analog values are known. Among them, those of the resistor string type and the R-2-R type using resistors are widely used as incorporated types in integrated circuits. They each have a configuration combining a plurality of resistors and a MOS transistor connected in series thereto such that the resistors are switched by switching elements controlled by a digital data, thereby to obtain a desire analog value.
In the configuration mentioned above, accuracy of resistors and characteristics of MOS transistors, such as ON resistance, large affect the accuracy of the analog output value. These parameters, however, vary independently from each other due to manufacturing fluctuation of integrated circuits. In general, therefore, they do not always exhibit designed values.
FIG. 4 is a circuit diagram that shows one of conventional DA converters, which has a resistor string type configuration connecting N resistors R1 through RN and a MOS transistor that are connected in series.
In the configuration of FIG. 4, resistors R1-RN have the function of dividing a voltage between a high potential reference voltage VrefH and a low potential reference voltage VrefL and generating analog voltages V1 through VN whereas the MOS transistor M1 plays the role of a switch that prevents a flow of a current from the high potential reference voltage VrefH to the low potential reference voltage VrefL and useless consumption of the power thereby while the DA converter is in rest. That is, when the DA converter is in rest, a power-down signal PDB maintains the drain current of the MOS transistor M1 substantially zero to prevent consumption of the current.
A digital input 12 is converted by a decoder 11 to a selection signal corresponding to the digital data, and one of switches SW1 through SWN associated with analog voltages V1-VN is selected. As a result, one of analog voltages V1-VN is selected and output as the analog output 13. Switches SW1-SWN can be realized by using MOS transistors.
Let all of resistance values of respective resistors R1-RN be Rr and let the ON resistance of the MOS transistor M1 be Ron. Then, the full scale voltage of the DA converter is
(VrefH-VrefL)xc3x97Rfxc3x97N/(Rrxc3x97N+Ron)xe2x80x83xe2x80x83(1)
In order to ensure that the full scale voltage is constant without manufacturing fluctuation among integrated circuits, it is necessary to design the ON resistance Ron to be sufficiently smaller than resistance Rrxc3x97N. To design the ON resistance Ron to be small, ratio of the channel width of the MOS transistor is required to be large relative to the channel length. This directly invites an increase of the chip area.
On the other hand, to ensure a high operating frequency of the DA converter, the time constant of the circuit itself has to be small. In this case, the resistance value of the resistors R1-RN must be small. For this purpose, ON resistance Ron of the MOS transistor M1 is required to be additionally smaller, which is an additional factor leading to a further increase of the chip area.
FIG. 5 is a circuit diagram that shows another conventional DA converter configured to divide a digital input signal to higher-order bits and lower-order bits and combine two DA converter blocks, one for higher-order bits and the other for lower-order bits.
In the configuration of FIG. 5, resistors RM1-RMN have function of dividing a voltage between a high potential reference voltage VrefH and a low potential reference voltage VrefL and generating analog voltages V1-VN whereas the MOS transistor M1 plays the role of a switch that prevents a flow of a current from the high potential reference voltage VrefH to the low potential reference voltage VrefL and thereby prevents useless consumption of the power while the DA converter is in rest. That is, when the DA converter is in rest, a power-down signal PDB maintains the drain current of the MOS transistor M1 substantially zero to prevent consumption of the current.
Connected to low-potential terminals of the resistors RM1-RMN-1 are MOS transistors MA1-MAN-1 that are selectively turned ON by selection signals Vg-VgN-1, and drain output is a secondary high potential reference voltage VH.
On the other hand, connected to low-potential terminals of the resistors M2-RMN are MOS transistors MB1-MBN-1 that are selectively turned ON by selection signals Vg1-VgN-1, and the drain output is a secondary low potential reference voltage VL.
A digital input 23 of the block of higher-order bits is converted to a selection signal Vg1-VgN-1 corresponding to the digital data by a decoder 21, and it is given to a MOS transistor MA1-MAN-1 and a MOS transistor MB1-MBN-1. As a result, a corresponding MOS transistor is turned ON. This results in the high-potential voltage of one of resistors RM2-RMN being selected and output as the secondary high potential reference voltage VH and the low-potential voltage of same being selected and output as the secondary low potential reference voltage VL.
The resistors RL1 through RLM have the function of dividing a voltage between the secondary high potential reference voltage VH and the secondary low potential reference voltage VL and generating analog voltages VL1-VLM.
A digital input 24 to the block of lower-order bits is converted to a selection signal corresponding to the digital data by a decoder 22, and one of switches SW1-SWM associated with respective analog voltages VL1-VLM is selected. As a result, one of analog voltages VL1-VLM is selected and output as the analog voltage value output 25. Switches SW1-SWM can be realized by using MOS transistors.
In summary, the DA converter having the configuration of FIG. 5 selects a voltage range which is data of a higher-order bit, and selects and outputs to the analog output 25 one of analog voltage values obtained by further dividing the selected voltage range with data of a lower-order bit.
For improving the accuracy of this circuit, it is necessary to maintain the ON resistance of MOS transistors MA1-MAN-1 and MOS transistors MB1-MBN-1 sufficiently smaller than the total of resistance values of resistors RL1-RLM of lower-order bits. For this purpose, the ratio of the channel width relative to the channel length must be large, that is, the channel width must be wider, and this inevitably increases the area occupied on an integrated circuit.
FIG. 6 is a circuit diagram that shows a still further conventional DA converter having a R-w-R type configuration.
As apparent from FIG. 6 as well, this DA converter is made up of resistors RC1-RCN-1, RD0-RDN and MOS transistors MD1-MDN and MD1B-MDNB.
MOS transistors MD1-MDN are each controlled by a signal VgD1-VgDN corresponding to digital inputs 31. On the other hand, MOS transistors MD1B-MDNB are controlled by signals VgD1B-VgDNB which are inversion signals of signals VgD1-VgDN. That is, they are so controlled that, while one is ON, the other is OFF, or while one is OFF, the other is ON, in each of associated pairs of MOS transistors MD1-MDN and MOS transistors MD1B-MDNB.
MOS transistors MD1-MDNB are connected to the high potential reference voltage VrefH whereas MOS transistors MD1B-MDNB are connected to the low potential reference voltage VrefL. Depending on a ON-OFF combination corresponding to the digital inputs 31, the high potential reference voltage VrefH or the low potential reference voltage VrefL is supplied to a connection point of serially connected resistors RD0, resistors RC1-RCN-1 through corresponding one of resistors RD1-RDN.
In the circuit of FIG. 6, when disregarding the ON resistance of each MOS transistor and setting the resistance of RDO-RDN to a value twice that of RC1-RCN-1, an analog value linearly responsive to the digital data from the digital inputs 31 should have been output to the analog output 32 in the calculated value. Actually, however, linearity is obtained by intentional adjustment taking account of ON resistance values of MOS transistors such that, when the resistance value of RC1-RCN-1 is Rr, the sum of the resistance value of RD1-RDN and the ON resistance value Ron of each MOS transistor becomes the resistance value 2Rr.
Actually, however, it is difficult to maintain a constant ratio between the ON resistance values Ron and the resistance values of the resistors. Practically, therefore, it is indispensable to design the MOS transistors to have sufficiently small ON resistance values Ron relative to the resistance values of the resistors such that any change in ratio does not affect the property of the DA converter. As a result, it is necessary to employ a large channel width of each MOS transistor relative to the channel length, and an increase of the occupied chip area is inevitable.
In the configurations of FIGS. 4, 5 and 6 that shows conventional configurations, NMOS transistors are employed as MOS transistors. However, even when they are PMOS transistors, or parallel connection of NMOS and PMOS transistors controlled by gate signals VgN and VgP as shown in FIG. 7, it is still necessary to employ a large channel width of each MOS transistor for reducing the ON resistance, and a corresponding chip area will be occupied.
As discussed above, because of configurations of realizing the function of a DA converter by combining a series of resistors and a MOS transistors on an integrated circuit, the conventional semiconductor devices could not accurately control the ratio of resistance values of the resistors and the ON resistance of the MOS transistor, and they were therefore compelled to design the MOS transistor to have a relatively low ON resistance, which inevitably increased the chip area of the integrated circuit.
Moreover, it is necessary to reliably cut off the high potential side and the low potential side of the power source, for example, to be isolated in voltage from each other, and it is important from viewpoints of the layout of wirings and other circuit designs to determine which element in which position should be used for the blocking. Furthermore, the blocking must be more reliable, and there arises the problem where the blocking element should be placed in positional relations with the high voltage side and the low voltage side of the power source, for example, and whether the element alone is sufficient for complete blocking.
It is therefore an object of the invention to overcome the problems involved in the conventional techniques and provide a DA converter replacing a series of resistors required to be highly accurate with transistors, noting that transistors can be controlled in resistance ratio therebetween with a relatively high accuracy on a common integrated circuit, and therefore capable of improving the accuracy of division of a voltage without increasing the chip area, having a margin in its circuit design, and capable of reliably cutting the voltage-dividing circuits.
To attain the object, according to an embodiment of the invention, there is provided a DA converter for dividing a reference voltage and outputting a partial voltage corresponding to an input digital data, comprising:
a set of resistive elements connected to the reference voltage and made up of serially connected resistive elements which are made of transistors, any number of the transistors at any position being usable for cutting the circuit off; and
a partial voltage extracting circuit for having a partial voltage corresponding to the input digital data be output from the set of resistive elements.
To attain the object, according to another embodiment of the invention, there is provided a DA converter for dividing a reference voltage and outputting a partial voltage corresponding to an input digital data, comprising:
a first set of resistive elements connected to the reference voltage, having a plurality of serially connected first resistive elements;
a first partial voltage extracting circuit for outputting a first partial voltage corresponding to one part of the input digital data be output from the first set of resistive elements;
a second set of resistive elements connected to the first partial voltage and having a plurality of serially connected second resistive elements; and
a second partial voltage extracting circuit for outputting a second partial voltage corresponding to the other part of the input digital data be output from the second set of resistive elements.
To attain the object, according to another embodiment of the invention, there is provided a DA converter for outputting a reference voltage as a partial voltage corresponding to an input digital data from an output end, comprising:
a first set of resistor elements including a plurality of resistive elements connected in series between a first reference voltage and the output end;
a first set of transistors including a plurality of first transistors each functioning as a switch and as a resistive element in the ON state thereof, each the first transistor being connected at one end to the first reference voltage and at the other end to one end of predetermined one of the resistive elements; and
a second set of transistors including a plurality of second transistors each functioning as a switch and as a resistive element in the ON state thereof, each the second transistor being connected at one end to the second reference voltage and at the other end to the other end of associated one of the first transistors, each the first transistor and associated one of the second transistors being controlled such that one of them turns ON whereas the other turns OFF, depending on the digital input.
To attain the object, according to another embodiment of the present invention, there is provided a DA converter for dividing a reference voltage and outputting a partial voltage corresponding to an input digital data providing a plurality of DA converter units serially connected to the reference voltage, each the DA converter, comprising:
a first set of resistive elements connected to the reference voltage and having a plurality of serially connected first resistive elements;
a first partial voltage extracting circuit for having a first partial voltage corresponding to one part of the input digital data be output from the first set of resistive elements;
a second set of resistive elements connected to the first partial voltage and having a plurality of serially connected second resistance elements; and
a second partial voltage extracting circuit for having a second partial voltage corresponding to the other part of the input digital data be output from the second set of resistive elements.